Design of an 8-bit time-mode cyclic ADC based on macro modeling

초록

This work presents a macro modeling approach for the time-mode cyclic ADC. The proposed ADC macro model is realized using the time-to-voltage converter (TVC) and the voltage-to-time converter (VTC) that are the key building blocks of time-mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time-mode ADC including parasitic capacitance, current source output resistance, switch on-resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8-bit time-mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated.

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